1. Field of the Invention
This invention relates to a digital data clocking system for asynchronous data transfer and, more specifically, to a recording channel data clock control loop without analog timing elements.
2. Discussion of the Related Art
A magnetic or optical recording channel is designed to accept data for storage and deliver the same on retrieval demand at a later time with reasonable access delay and without errors. Self-clocking modulation codes are employed to ensure an adequate minimum rate of signal transitions for clock synchronization during data retrieval without exceeding the maximum transition storage density of the magnetic or optical medium during data storage. Such modulation codes are run-length-limiting (RLL) codes that represent a one-to-one mapping of binary data into a constrained binary sequence that is then recorded on the recording medium in the form of a modified Non-Return-to-Zero (NRZI) waveform.
In a NRZI waveform, the maximum and minimum number of spaces between consecutive transitions correspond to the maximum and minimum run lengths of zeros between two consecutive ones in the corresponding binary sequence, as is known in the art. Thus, such modulation codes fall within the class of RLL codes characterized by the parameters (d,k) where d represents the minimum and k represents the maximum number of zeros between two consecutive ones in the coded sequence. These codes are the result of a steady evolution of waveform design coupled with improvements in magnetic and optical recording channels, including improved clocking and signal-detection processes.
In a recording channel, the read clocking function is the key to restoring digital data following transition detection. The read clocking function separates the synchronous data clock signal from the self-clocking data signal in the recording channel. It is usually performed by a phase-locked oscillator (PLO), which regenerates the synchronous data clock waveform in response to the flow of self-clocking signal waveform peaks from the magnetic or optical transition detector. Although this phase control loop can be primarily digital, as with a digital phase-locked loop (DPLL), some analog components are necessary. Even in a DPLL, the digitally-controlled oscillator (DCO) employs analog components. Ideally, a digital implementation without analog components is desired because it permits an inexpensive and efficient monolithic device to perform accurate read clocking without calibration drift or adjustment.
Practitioners have suggested progressive improvements to the DPLL known in the art. A comprehensive survey of the DPLL art is provided by William C. Lindsay et al, "A Survey of Digital Phase-Locked Loops", Proc. IEEE, Vol, 69, pp. 410-431, Apr. 1981. These improvements are motivated by the several disadvantages of the analog clock recovery procedures known in the DPLL art. The most obvious disadvantage is that the VCO used to control the clock frequency is an analog component. The analog VCO gain and operating points may depend upon the manufacturing processes. The components may be relatively costly to build and calibrate, thereby offsetting the cost advantage of a digital system implementation. Another disadvantage is the phase error correction delays inherent within a VCO control loop. Tightening the control loop requires tighter restrictions on variations in the input data rate. This may not be feasible in a typical magnetic tape product or in optical data storage systems having variable linear read and write speeds. Moreover, equalization and detector improvements in the recording art may increase the PLL feedback loop delays and exacerbate the problem.
In U.S. Pat. No. 4,987,373, David C. Soo discloses a PLL circuit that uses analog sample detection techniques in his phase detector and the loop filter circuitry in an attempt to avoid some of the difficulties inherent in analog components. However, Soo requires an analog clock generator to drive his sampled-data phase detector circuit.
In U.S. Pat. No. 4,797,845, Eduard F. Stikvoort discloses a PLL coefficient generator for generating deviation signals for use in a sample rate converter with a non-rational sampling ratio. Stikvoort uses synthetic low-rate clock pulses in addition to the normal phase detector clock pulses to make his phase error correction process less subject to the common weaknesses of analog component problems. However, application of his teachings is limited to sample rate converters.
In U.S. Pat. No. 4,912,729, Antonia C. Van Rens et al disclose a DPLL circuit comprising a discrete-time oscillator corrected in phase and frequency to track a sampled input signal. Although their PLL circuit can be constructed entirely by means of digital elements, they use a discrete-time oscillator that drifts rapidly in the absence of frequent input transitions during longer RLL codes, which prevents application of their invention to many useful asynchronous channels.
Thus, despite numerous efforts in the art, there still exists a clearly-felt need for a purely digital implementation of a recording channel clock controller for regenerating and restoring digital data after detection. The related unresolved problems and deficiencies are clearly felt in the art and are solved by this invention in the manner described below.